As active device dimensions get smaller, it is desirable to reduce the thickness of a gate insulating layer in such devices. The push toward thinner insulating layers is expected to limit the use of the currently popular conventional gate insulting layer, silicon dioxide. This follows because at some point of diminishing thickness, about 1 to about 1.2 nm, the leakage of current through the silicon dioxide insulating layer will become unacceptably high and adversely affect device performance.
One proposed solution is to use gate insulating layers composed of dielectric materials with a higher dielectric constant than that of silicon dioxide. Such materials, termed high K dielectrics, have superior insulating characteristics compared to silicon dioxide for equivalent thicknesses, for example, by allowing less leakage current. There are, however, a number of problems with forming gate insulating layers composed of dielectric materials. It is difficult, for example, to deposit high K dielectric materials by chemical vapor deposition directly on hydrogen-terminated silicon substrates, because such materials are not reactive enough to bond directly to silicon.
To facilitate deposition, typically an underlying layer of silicon hydroxide or oxide is first formed between the silicon substrate and the high K dielectric material. Formation of a silicon dioxide layer of about 1 nm or thicker, defeats the purpose of switching to a high K dielectric, because the presence of the thick silicon dioxide layer again gives rise to the above-mentioned problems. Alternatively, the formation of a silicon dioxide layer between the substrate and the dielectric layer may be an unavoidable by-product of the conventional techniques used to deposit the dielectric material and underlying layer on the silicon substrate. Techniques, such as metal-organic, chemical vapor deposition (CVD), rapid thermal CVD, atomic layer CVD, sputtering and electron-beam evaporation, all result in the formation of an undesired silicon dioxide layer.
One approach, for example, is using atomic layer deposition (ALD) to expose a hydrogen-terminated silicon surface to an oxygen source, such as water, to form an oxide layer, followed by the deposition of a high K dielectric precursor. Brief alternating exposures of the substrate to the oxygen source and the high K dielectric precursor result in the formation of a metal oxide layer comprising the high K dielectric. The high K dielectric layer, however, also contains an unacceptably thick (about 1 nm) silicon dioxide layer, and semiconductor devices having such insulating layers will not achieve an equivalent oxide thickness of less than 1 nm, as is desired for CMOS scaling.
Accordingly, what is needed in the art is a semiconductor device and method of manufacturing thereof that does not exhibit the limitations of the prior art.